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3 v/5 v, 16-bit nano dac tm d/a with 10 ppm/c max on-chip reference in sot-23 prelim inary technical data ad5660 rev. pr j in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features low power single 16-bit nano dac 12-bit accu racy gu aranteed on-chip 1.25/2.5 v, 1 0 ppm/c reference tiny 8- lead sot-23/msop package power-down to 200 n a @ 5 v, 50 na @ 3 v 3 v/5 v single p o wer supply guarantee d 1 6 - bit monotonic by design power-on-reset to zero/midscale three power-d o wn functions serial interf ace with schmitt-t r iggered input s rail-to-rail ope r ation sync interrupt facility applic ati o ns processcontr ol data acq u isitio n systems portable batter y -powered inst ruments digital gain and offset adjustment programmable voltage an d current sources programmable attenuators fi g u r e 1 . general description the ad5660 p a r t s a r e a m e m b er o f th e na no da c f a m i l y o f de vices. the y a r e lo w p o w e r , sin g le , 16-b i t b u f f er e d v o l t a g e-o u t d a c s , g u ar a n te e d monoton i c b y de s i g n . the ad5660x-1 o p era t e f r o m a 3 v sin g le s u p p ly f e a t ur in g a n in t e r n al r e f e r e nce o f 1.25 v a n d a n in t e r n al ga in o f 2. th e ad5660x-2/3 op era t e f r o m a 5 v sin g le s u p p l y f e a t ur in g an in t e r n al r e f e r e nce o f 2.5 v a nd a n in t e r n al ga in o f 2. e a c h r e fer e n c e has a 10 p p m / c max t e m p era t ur e co ef f i cien t. th e r e f e r e n c e a s s o c i at e d w i t h e a c h p a r t i s av a i l a b l e at t h e r e f o u t pi n . t h e p a r t i n c o r p or a t e s a p o we r - on re s e t c i rc u i t t h a t e n su re s t h at th e d a c o u t p u t p o w e rs u p t o 0 v (ad5660x-1/2) o r mids cale (ad5660x-3) and r e ma in s t h ere un til a valid wr i t e ta k e s p l ace . t h e p a r t c o n t a i n s a p o w e r- d o w n f e atu r e t h at r e du c e s t h e c u r r e n t co n s um p t io n o f th e de vice t o 200 na a t 5 v and p r o v ides s o f t wa r e s e le c t ab le o u t p u t lo ads while in p o w e r - do wn m o de . the ad5660 us es a v e rs a t ile three-wir e s e r i al in t e r f ace tha t o p e r at e s at c l o c k r a t e s u p t o 3 0 m h z a n d i s c o mp at i b l e w i t h s t anda r d s p i?, qs p i ?, mi cr o w ire? an d ds p in t e r f ace st anda r d s. i t s on-ch i p p r e c ision o u t p u t am plif ier a l lo ws ra i l -t o- ra il o u t p u t s w ing t o be achieved. the lo w p o w e r co n s um p t io n o f t h is p a r t in n o r m a l o p era t ion m a k e s i t i d eall y s u i t e d t o po r t a b l e ba t t e r y o p e r a t ed e q ui p m en t . the p o w e r co n s um p t ion is 0.7 mw a t 5 v r e d u cin g t o 1 w in p o w e r - do w n mo de. the ad5660 is desig n e d wi t h new tec h n o log y a nd is the n e xt g e n e ra ti o n t o th e a d 53xx fa mil y . product highlights 1. 16-b i t d a c; 12-b i t a c c u rac y g u a r a n t e e d . 2. on-c hi p 1.25/2. 5 v , 10 p p m /c max ref e r e nce . 3. a v a i la b l e in 8-le ad sot - 23 and 8-lead mso p p a c k a g e . 4. p o w e r - on res e t t o 0 v o r m i ds cale . 5. p o w e r - dow n c a p a b i l i ty . w h e n p o w e r e d dow n , t h e d a c typ i cal l y co ns um es 50 na a t 3 v a nd 200 n a a t 5 v . 6. 10 s s e t t lin g t i me . related de vices part no. description ad5620/ad564 0 3 v/5 v 12-/14-bit dac with inte rnal ref in sot-23 ad5662 2.7v to 5.5 v, 16 -bit dac in sot- 23, external refere n c e
ad5660 preliminary technical data rev. prj page 2 of 20 table of contents ad5660x-2/3Cspecifications ......................................................... 3 ad5660x-1Cspecifications.............................................................. 5 timing characteristics..................................................................... 7 pin configuration and function descriptions............................. 8 absolute maximum ratings............................................................ 9 esd caution.................................................................................. 9 terminology .................................................................................... 10 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 14 d/a section................................................................................. 14 resistor string ............................................................................. 14 output amplifier ........................................................................ 14 serial interface ............................................................................ 14 sync interrupt .......................................................................... 15 power-on reset.......................................................................... 15 power-down modes .................................................................. 15 microprocessor interfacing....................................................... 15 applications..................................................................................... 17 using ref19x as a power supply for ad5660 ....................... 17 bipolar operation using the ad5660 ..................................... 17 using ad5660 with an opto-isolated interface..................... 17 power supply bypassing and grounding................................ 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history revision prj: preliminary
preliminary technical data ad5660 rev. prj | page 3 of 20 ad5660x-2/3Cspecifications v dd = 4.5 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 1. parameter a grade b grade c grade unit b version 1 conditions/comments static performance 2 resolution 16 16 16 bits min relative accuracy 32 16 16 lsb max see figure 4 differential nonlinearity 1 1 1 lsb max guaranteed monotonic by design. see figure 5. zero code error +5 +5 +5 mv typ all zeroes loaded to dac +20 +20 +20 mv max register. see figure 8. full-scale error ?0.15 ?0.15 ?0.15 % of fsr typ all ones loaded to dac ?1.25 ?1.25 ?1.25 % of fsr max register. see figure 8 gain error 1.25 1.25 1.25 % of fsr max zero code error drift 3 20 20 20 v/c typ gain temperature coefficient 5 5 5 ppm typ f fsr/c output characteristics 3 output voltage range 0 0 v min v dd v dd v dd v max output voltage settling time 8 8 8 s typ to 0.003% fsr 0200 h to fd00 h 10 10 10 s max r l = 2 k?; 0 pf ad5660 preliminary technical data rev. prj page 4 of 20 parameter a grade b grade c grade unit b version 1 conditions/comments power requirements v dd 4.5 4.5 4.5 v min all digital inputs at 0 v or v dd 5.5 5.5 5.5 v max dac active and excluding i dd (normal mode) load current v dd = 4.5 v to +5.5 v 0.5 0.5 0.5 ma typ v ih = v dd and v il = gnd v dd = 4.5 v to +5.5 v 1 1 1 ma max v ih = v dd and v il = gnd i dd (all power-down modes) v dd = 4.5 v to +5.5 v 0.2 0.2 0.2 a typ v ih = v dd and v il = gnd v dd = 4.5 v to +5.5 v 1 1 1 a max v ih = v dd and v il = gnd power efficiency i out /i dd 89 89 89 % i load = 2 ma, v dd = 5 v 1 temperature ranges are as follows: b version: -40c to +105c, typical at 25c. 2 linearity calculated usin g a reduced code ra nge of 485 to 64714. output unloaded. 3 guaranteed by design and characterization, not production tested.
preliminary technical data ad5660 rev. prj | page 5 of 20 ad5660x-1Cspecifications v dd = 2.7 v to 3.6 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2. parameter a grade b grade c grade unit b version 4 conditions/comments static performance 5 resolution 16 16 16 bits min relative accuracy 32 16 16 lsb max see figure 4 differential nonlinearity 1 1 1 lsb max guaranteed monotonic by design. see figure 5. zero code error +5 +5 +5 mv typ all zeroes loaded to dac +20 +20 +20 mv max register. see figure 8. full-scale error ?0.15 ?0.15 ?0.15 % of fsr typ all ones loaded to dac ?1.25 ?1.25 ?1.25 % of fsr max register. see figure 8. gain error 1.25 1.25 1.25 % of fsr max zero code error drift 6 20 20 20 v/c typ gain temperature coefficient 5 5 5 ppm typ of fsr/c output characteristics 3 output voltage range 0 0 v min v dd v dd v dd v max output voltage settling time 8 8 8 s typ to 0.003% fsr 0200 h to fd00 h 10 10 10 s max r l = 2 k?; 0 pf ad5660 preliminary technical data rev. prj page 6 of 20 parameter a grade b grade c grade unit b version 4 conditions/comments power requirements v dd 2.7 2.7 2.7 v min all digital inputs at 0 v or v dd 3.6 3.6 3.6 v max dac active and excluding i dd (normal mode) load current v dd = 2.7 v to 3.6 v 0.5 0.5 0.5 ma typ v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 1 1 1 ma max v ih = v dd and v il = gnd i dd (all power-down modes) v dd = 2.7 v to 3.6 v 0.2 0.2 0.2 a typ v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 1 1 1 a max v ih = v dd and v il = gnd power efficiency i out /i dd i load = 2 ma, v dd = 3 v 4 temperature ranges are as follows: b version: -40c to +105c, typical at 25c. 5 linearity calculated usin g a reduced code ra nge of 485 to 64714. output unloaded. 6 guaranteed by design and characterization, not production tested.
prelim inary technical data ad5660 r e v. prj | pa ge 7 o f 20 timing characteristics a l l in p u t sig n a l s a r e sp e c if ie d wi t h t r = t f = 1 n s /v (10 % t o 90 % o f v dd ) a n d t i m e d f r o m a vol t a g e le vel o f (v il + v ih )/2. s e e f i gur e 2. v dd = 2.7 v t o 5 . 5 v ; al l s p ec if ic a t io n s t min to t max , u n l e ss ot he r w i s e note d. limit at t min , t ma x parameter v dd = 2.7 v to 3 . 6 v v dd = 3.6 v to 5 . 5 v unit conditions/comments t 1 1 50 33 ns min sclk cycle time t 2 13 13 ns min sclk high time t 3 13 13 ns min sclk low time t 4 13 13 ns min sync to sclk falling edge setup tim e t 5 5 5 ns min data setup tim e t 6 4.5 4.5 ns min data hold time t 7 0 0 ns min sclk falling edge to sync rising ed ge t 8 50 33 ns min minimum sync high time t 9 13 13 ns min sync rising edge to sclk fall ignore t 10 0 0 ns min sclk falling edge to sync fall ignor e 1 ma xi m u m s c lk fre q uen c y i s 30 mh z a t v dd = 3.6 v to 5.5 v and 20 mhz at v dd = 2.7 v to 3.6 v. f i gure 2. s e r i a l w r ite o p er ati o n
ad5660 prelim inary technical data r e v. prj pa ge 8 of 20 pin conf iguration and fu nction descriptions f i gure 3. pin config ur ation ta ble 3. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 1 v dd power supply in put. t h ese parts can be oper a te d from 2.5 v to 5.5 v and v dd should be d e couple d to gnd. 2 v ref o u t reference voltage output. 3 v fb feedback connection for the output amplifier. 4 v ou t analog output voltage from dac. the output a m plifier ha s rail to rail oper a tion . 5 sync level triggered control in put (active low). this i s the frame sync hronizat i o n sign al for the input data. when sync goes low , it ena b les the in put shift register and d a ta is transferred in on the falli ng ed ges of the follo wing clock s . t h e dac is upd a ted follo wing the 24th clock cycle unle ss sync is taken high before this edge in which case the risi ng ed ge of sync acts as a n interrupt and the write seque n ce is ignored by the dac. 6 sclk serial clock input. data is cl ocked into the input shift regi ster on the falling edge of the serial cl ock input. data can be transferred at rates up to 30 mhz. 7 d in serial data inpu t. this device has a 24-bit shift register. data is clocked into the regi ster on the falling edge of the serial c l ock i n put. 8 gnd ground reference point for all c i rcuitry on the part.
prelim inary technical data ad5660 r e v. prj | pa ge 9 o f 20 absolute maximum ratings t a = +25c unles s o t h e r w ise no t e d . table 4. p a r a m e t e r r a t i n g v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v v ou t to gnd ?0.3 v to v dd + 0.3 v operating tem p erature range industrial (b versio n) ?40c to +105c storage temperature range ?65c to +150c j u nction temperature (t j max) 150c sot-23 package power dissi pati on ( t j max ? t a )/ ja ja thermal impedance 240c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5660 preliminary technical data rev. prj page 10 of 20 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 4. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 5. zero-code error zero-code error is a measure of the output error when zero code (0000hex) is loaded to the dac register. ideally the output should be 0 v. the zero-code error is always positive in the ad5660 because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in mv. a plot of zero-code error vs. temperature can be seen in figure 8. full-scale error full-scale error is a measure of the output error when full-scale code (ffff hex) is loaded to the dac register. ideally the output should be v dd C 1 lsb. full-scale error is expressed in percent of full-scale range. a plot of full-scale error vs. temperature can be seen in figure 8. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed as a percent of the full-scale range. tot a l un a dju s te d e r ror total unadjusted error (tue) is a measure of the output error taking all the various errors into account. a typical tue vs. code plot can be seen in figure 6. zero-code error drift this is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in ( ppm of full-scale range)/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv secs and is measured when the digital input code is changed by 1 lsb at the major carry transition (7fff hex to 8000 hex). see figure 21. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa.
prelim inary technical data ad5660 r e v. prj | pa ge 11 o f 20 typical perf orm ance cha r acte ristics f i g u re 4. t y pic a l in l plot f i g u re 5. t y pic a l d n l pl ot f i gure 6. t y pic a l t o tal u n adjus t ed e rro r p l ot f i gure 7. inl e rror and d n l e rror v s . t e mper atur e f i gure 8. zero -s c a l e e rror and f u ll- s c a l e e r r o r v s . t e mpe r a t ur e fi g u r e 9 . i dd his t og r a m wit h v dd = 3 v and v dd = 5 v
ad5660 prelim inary technical data rev. prj page 12 of 20 f i gure 10. s o urc e and sink curr ent capabilit y with v dd = 3 v f i gure 11. s o urc e and sink curr ent capabilit y with v dd = 5 v f i gure 12. sup p l y current v s . code f i gure 13. sup p l y current v s . t e mper at ur e f i gure 14. sup p l y current v s . sup p ly v o ltag e f i gure 15. p o wer - d o wn cur r ent vs. su p p ly v o ltage
prelim inary technical data ad5660 r e v. prj | pa ge 13 o f 20 f i gure 16. sup p l y current v s . l o gic i n p u t v o ltag e f i g u re 17. f u ll- s c al e s e t t ling ti me f i g u re 18. h a lf -s c a l e s e t t ling ti me f i g u re 19. p o wer - o n r e s e t to 0v f i g u re 20. e x it ing p o wer - d o wn ( 8 00 h e x l oaded) f i g u re 21. d i g i t a l- t o -a na log g l i t ch i m puls e
ad5660 prelim inary technical data rev. prj page 14 of 20 theory of operation d/a secti o n the ad5660 d a c is fa b r ic a t e d o n a cm os p r o c es s. th e a r c h i t ec t u r e co nsis ts o f a s t r i n g d a c f o l l o w ed b y a n o u t p u t b u f f er a m p l if ier . the p a r t s inc l ude a n in ter n al 1.25 v/2.5 v , 1 0 ppm / c re f e re nc e w i t h an i n t e r n a l g a i n of t w o . f i g u re 2 2 sh o w s a b l o c k d i a g ram o f t h e d a c a r chi t e c t u r e . f i gu r e 2 2 . d a c a r ch i t ectu r e sin c e t h e i n p u t co din g t o t h e d a c is s t ra ig h t b i na r y , t h e ide a l out p ut vol t ag e i s g i ve n b y : ? ? ? ? ? ? = 65536 2 d xvref v out w h er e d = th e deci m a l eq ui v a len t o f th e b i n a r y cod e th a t i s lo aded t o the d a c r e g i s t er ; i t c a n ra n g e f r o m 0 t o 65535. f i gur e 2 3 . resi st or str i ng resistor string the r e sist o r st r i n g s e c t ion is sho w n i n f i gur e 2 3 . i t is sim p ly a s t r i n g o f r e sis t o r s, eac h o f val u e r . th e co de lo aded t o t h e d a c r e g i s t er det e r m in es a t w h ich n o de o n t h e st r i n g t h e v o l t a g e is t a p p e d o f f t o b e fe d in t o t h e o u t p u t am plif ier . th e v o l t a g e is t a pp e d of f by cl o s i n g one of t h e s w itc h e s c o n n e c t i ng t h e st r i ng t o t h e am plif ier . b e ca us e i t is a st r i n g o f r e sist o r s, i t is g u ar an t e e d monoton i c . outpu t am plifier t h e o u t p u t b u f f er a m p l if ier is ca p a b l e o f g e n e ra tin g rail-t o-rail vo lt age s on it s o u tput w h i c h g i v e s an output r a n g e of 0 v to v dd . i t is ca p a b l e o f dr i v in g a lo ad of 2 k? in p a ral l e l wi th 1000 pf t o gnd . th e s o urce an d sink c a p a b i li t i es o f t h e ou t p ut a m pl if ier ca n be s e en in f i gur e 10 a nd f i g u r e 11. th e s l ew ra t e is 1 v/ s w i t h a half- scale set t lin g tim e o f 8 s w i t h th e o u t p u t unloa d ed . serial interface the ad5660 has a 3-wir e s e r i al in t e r f ace ( sy n c , s c l k a n d d i n), whic h is co m p a t i b le wi th s p i, qs p i and mi cro w i r e in t e r f ace st andar d s as w e l l as most ds p s . s e e f i gur e 2 fo r a t i min g d i a g ram o f a ty p i ca l wr i t e s e q u e n ce. the wr i t e s e q u e n ce b e g i n s b y b r in g i n g t h e sy n c lin e lo w . d a ta f r o m t h e d i n li n e is clo c k e d i n to t h e 24- b i t shif t r e g i st er o n t h e fa l l in g e d ge o f s c lk. t h e s e r i a l clo c k f r e q uen c y ca n b e as hig h as 30 mh z, mak i n g the ad5660 co m p a t i b le wi th hig h sp ee d d s p s . on th e 24th falli n g c l oc k ed g e , th e las t da ta b i t i s c l ock e d in and t h e p r og ra mme d f u n c t i o n is exe c u t e d , t h a t is, a chan ge in d a c r e g i s t er con t en ts and/o r a c h a n g e in t h e mo de o f o p era t ion. a t t h is st a g e , t h e sy n c lin e ma y b e k e p t lo w o r be b r o u gh t hi gh . i n e i th e r ca se , i t m u s t be b r o u gh t h i gh f o r a minim u m o f 33 n s bef o r e t h e next wr i t e s e q u en ce s o tha t a fallin g edg e o f sy n c ca n i n i t i a t e t h e n e xt wr i t e s e q u en c e . sin c e th e sy n c b u f f er dra w s m o r e c u r r en t w h en v in = 2.4 v tha n i t do es w h e n v in = 0.8 v , sy n c s h o u ld be idle d lo w b e tw e e n wr i t e seq u en ces f o r e v en lo w e r p o w e r o p era t io n o f t h e p a r t . a s is me n t i o ne d ab ove, howe ve r , i t m u st b e b r ou g h t hi g h ag ai n j u st b e fo r e t h e n e xt wr i t e s e q u e n ce. inpu t shift register the in p u t shif t r e g i s t er is 24 b i ts wide (s ee f i gu r e 24). th e f i rs t six b i ts a r e d o n t ca r e s. th e n e xt tw o a r e co n t r o l b i ts th a t co n t r o l w h ich m o d e o f o p era t i o n t h e p a r t is in (n o r ma l mo de o r a n y o n e o f t h r e e p o w e r - do w n m o des). th ere is a m o r e co m p lete des c r i p t io n o f t h e va r i o u s m o des i n t h e p o w e r - d o w n m o des s e c t ion. the n e xt sixt e e n b i ts a r e t h e da t a b i ts. th e s e a r e t r a n sfer r e d t o t h e d a c r e g i s t er o n t h e24t h fal l in g e d g e o f sclk.
prelim inary technical data ad5660 r e v. prj | pa ge 15 o f 20 f i gure 2 4 . input regi st er co ntents sync interrupt i n a n o rm al w r i t e seq u en ce , th e sy n c lin e is k e p t lo w f o r a t le ast 24 fa l l in g e d ges o f sclk and t h e d a c is up d a te d on t h e 24th fal l in g e d ge . h o w e v e r , if sy n c i s b r o u gh t hi gh be f o r e th e 24t h fa l l in g e d ge t h is ac ts as an in t e r r u p t t o t h e wr i t e s e q u e n ce. the s h if t r e g i s t e r is r e s e t a nd t h e wr i t e s e q u e n c e is s e en as in valid . n e i t h e r a n u p da te o f the d a c r e g i st er co n t en ts o r a cha n g e i n t h e op era t i n g m o de o c c u rss e e f i g u r e 27. power-on reset the ad5660 famil y co n t ain s a p o w e r - o n r e s e t cir c ui t tha t co n t r o ls th e o u t p u t v o l t a g e d u r i n g p o w e r - u p . th e ad5660x-1 /2 d a c o u t p u t p o w e rs u p t o zer o v o l t s an d t h e ad5660x-3 d a c o u t p ut p o w e rs u p t o mids cal e . the o u t p u t r e ma in s t h er e un t i l a valid wr i t e s e q u en c e is made t o t h e d a c. this i s us ef u l in a p plic a t ion s w h er e i t is i m p o r t an t t o k n o w t h e st a t e o f t h e o u t p ut o f t h e d a c w h i l e i t is i n t h e p r o c ess o f p o w e r i n g u p . power-down modes the ad5660 con t a i n s f o ur s e p a ra t e m o des o f o p era t ion. th es e mo d e s are s o f t w a re - p ro g r am m a bl e by s e tt i n g t w o bit s ( d b 1 7 a nd d b 16) in t h e co n t r o l r e g i s t e r . t a b l e 5 sh o w s h o w t h e s t a t e o f t h e b i ts co r r es p o n d s t o t h e m o de o f o p era t ion o f t h e de vi ce . table 5. modes of operation for the ad566 0 db17 db16 operating mode 0 0 normal ope rati on power down m o d e s 0 1 1 k? to gnd 1 0 100 k? to gnd 1 1 three state w h en b o t h b i ts a r e s e t t o 0, t h e p a r t w o rks n o r m al l y wi t h i t s n o r m al p o w e r c o n s um p t io n o f 250 a a t 5 v . h o w e v e r , f o r th e thr e e p o w e r - do wn m o des, t h e su p p l y c u r r en t fal l s t o 200 na a t 5 v (50 na a t 3 v). n o t o n l y do es t h e su p p l y c u r r en t fal l b u t t h e output st age i s a l s o i n te r n a l ly s w itc h e d f r om t h e output of t h e am pl i f i e r to a re s i stor ne t w or k o f k n ow n v a lu e s . t h i s h a s t h e ad van t a g e t h a t t h e o u t p ut i m p e dan c e o f t h e p a r t is kn own w h i l e t h e p a r t is in p o w e r - do w n m o de . ther e a r e t h r e e dif f er en t opt i ons . t h e output i s c o n n e c te d i n te r n a l ly to g n d t h rou g h a 1 k? r e sis t o r , a 100 k? r e sis t o r o r i t is lef t o p en-cir c u i t e d (t hr ee-s t a te). th e o u t p u t s t a g e is ill u s t ra t e d in f i gur e 25. f i gure 25. o u tput s t age d u r i ng p o wer-d o wn the b i as g e n e ra t o r , t h e o u t p u t am plif ier , t h e r e sis t o r s t r i n g and o t h e r ass o cia t ed lin e a r cir c ui tr y a r e al l s h u t do wn w h en t h e po w e r - d o wn m o d e i s a c ti va t e d . h o w e v e r , th e co n t en t s o f th e d a c r e g i s t er a r e una f fe c t e d w h en in p o w e r - dow n . th e t i me t o exi t p o w e r - down is typ i cal l y 2.5 s f o r v dd = 5 v a nd 5 s f o r v dd = 3 v . s e e f i gur e 20 f o r a p l o t . microprocessor interfacing ad5660 to adsp-2101/adsp-2103 interface f i gur e 26 s h o w s a s e r i al in t e r f ac e betw een t h e ad5660 a nd t h e ads p -2101/ads p -2103. th e ads p -2101 /ads p - 2103 sh o u ld b e s e t u p t o o p e r a t e i n t h e s p or t t r a n smi t al t e r n a t e f r a m in g m o de . th e ads p -2101/ads p -2 103 s p o r t is p r og ra mm ed t h rou g h t h e sp or t c o n t ro l re g i ste r a n d s h ou l d b e c o n f i g u r e d as fol l o w s: in t e r n a l clo c k o p er a t io n, ac t i ve lo w f r a m ing, 24-b i t w o r d len g t h . t r a n smissio n is in i t i a te d b y wr i t ing a w o r d t o t h e tx r e g i s t er a f t e r t h e s p or t has b e e n enab le d . f i gur e 2 6 . ad56 60 t o adsp -2 10 1/ adsp -2 10 3 int e r f a c e
ad5660 prelim inary technical data rev. prj page 16 of 20 f i gure 27. sync in terrupt f a ci li t y ad5660 to 68hc11/68l1 1 interface f i gur e 28 s h o w s a s e r i al in t e r f ac e betw een t h e ad5660 a nd t h e 68h c11/68l11 micr o c o n tr ol ler . sck o f th e 68 h c 11/68l11 dr i v es t h e s c l k o f t h e ad566 0, w h i l e t h e mo s i o u t p u t dr i v es t h e s e r i al da t a li n e o f t h e d a c. the sy n c sig n a l is der i ve d f r o m a p o r t line (pc7). t h e s e t u p co n d i t io n s f o r co r r ec t o p era t ion o f this in t e r f ace a r e as f o l l o w s: th e 68 h c 11/68l11 s h o u ld b e co nf igur ed s o tha t i t s cpo l b i t is a 0 a nd i t s cp h a b i t i s a 1. w h en da ta i s be in g tra n sm i t t e d t o t h e d a c , th e sy n c lin e is ta k e n lo w (pc7). w h en th e 68 h c 11/68 l 11 is co nf igur ed as a b o v e , da ta a p p e a r in g on the m o s i o u t p u t is valid o n t h e fal l in g edg e o f s c k. s e r i al da t a f r o m th e 68 h c 1 1 / 68l11 is tra n smi t t e d in 8 - b i t b y t e s wi th onl y eig h t fal l in g c l o c k e d g e s occurri n g i n th e tra n sm i t c y c l e . da t a i s tra n smi t t e d ms b f i r s t . i n o r der t o lo ad da ta t o th e ad5660, pc7 is lef t lo w a f t e r th e f i rst eig h t b i ts ar e t r a n sfer r e d , a nd a s e co nd s e r i a l wr i t e o p er a t ion is p e r f o r m e d to t h e d a c a nd pc7 is t a k e n hig h a t t h e end o f t h is p r o c e d ur e. f i gur e 2 8 . ad56 60 t o 6 8 h c 11 /68 l 11 int e r f a c e ad5660 to 80c51/80l5 1 interface f i gur e 29 s h o w s a s e r i al in t e r f ac e betw een t h e ad5660 a nd t h e 80c51/80l51 micr o c o n tr ol ler . th e s e t u p f o r the in t e r f ace is as f o l l o w s: t x d o f th e 80c51 /80l 51 dr i v es sclk o f th e ad5660, w h i l e r x d dr i v es t h e s e r i al da t a li n e o f t h e p a r t . th e sy n c sig n a l is a g a i n d e r i ve d f r o m a b i t p r o g r a mma b l e p i n on t h e p o r t . i n this c a s e p o r t lin e p3 .3 is us ed . w h en da t a is t o be tra n smi t t e d t o t h e ad5660, p3. 3 is tak e n lo w . th e 80c51 /80l5 1 tra n smi t s da t a onl y in 8-b i t b y t e s; th us o n l y eig h t fal l in g c l o c k edg e s o c c u r in t h e tran smi t c y c l e . t o lo ad da t a to th e d a c, p3.3 i s l e f t l o w af te r t h e f i rst e i g h t bi t s are t r ans m it t e d, an d a s e c o n d wr i t e c y cle is in i t ia t e d t o t r a n sm i t t h e s e cond b y t e o f d a t a . p3.3 i s t a ke n h i g h f o l l ow i n g t h e c o m p l e t i on of t h i s c y cl e. t h e 80c51/80l51 ou t p u t s the s e r i al da ta in a f o r m a t which has t h e ls b f i rs t. th e ad5660 r e q u ir es i t s da ta wi th t h e ms b as t h e f i rst b i t r e cei v e d . the 80c51/80l51 tra n smi t r o u t ine s h o u l d ta k e this in t o acco u n t. f i g u re 29. a d 5 6 6 0 to 80c 51 int e r f ace ad5660 to microwire interface f i gur e 30 s h o w s a n in t e r f ace betw een t h e ad53 20 a nd an y mi cro w i r e c o m p a t i b le de vic e . s e r i a l da t a is shif te d o u t on th e fallin g ed ge o f th e se ri al c l o c k a n d i s c l ock e d i n t o th e ad5320 o n t h e r i sin g edg e o f th e s k . f i gur e 3 0 . ad56 60 t o micr ow ire inter f a c e
prelim inary technical data ad5660 r e v. prj | pa ge 17 o f 20 appli c ations using ref1 9x as a power supply for ad56 60 b e ca us e the s u p p l y c u rr en t r e q u ir ed b y the ad5 660 is extr em e l y lo w , a n al t e r n a t iv e o p t i o n is t o us e a ref19x v o l t a g e r e fer e n c e (ref195 f o r 5 v o r ref193 f o r 3 v) t o s u p p l y th e r e q u ir e d v o l t a g e t o t h e p a r t s e e f i gur e 31. this is es p e c i al l y us ef u l if t h e p o w e r s u p p l y is q u i t e n o i s y o r if t h e sys t em su ppl y v o l t a g es a r e a t s o m e val u e o t h e r than 5 v o r 3 v , f o r exa m p l e , 15 v . th e ref19x wil l o u t p u t a st ead y su p p l y v o l t a g e f o r th e ad5660. i f th e lo w dr o p o u t ref195 is us ed, th e c u r r en t i t needs t o s u p p l y t o th e ad5660 is 250 a. this is wi th n o lo ad on the o u t p u t o f th e d a c. w h en th e d a c o u t p u t is lo aded , the ref195 als o n e e d s t o s u p p l y t h e c u r r en t t o t h e lo ad . the t o t a l c u r r en t r e q u ir e d ( w i t h a 5 k? lo ad o n t h e d a c o u t p u t ) is ( ) ma v a 25 . 1 5 / 5 250 = ? + the lo ad r e gu l a tio n o f th e ref195 is typ i cal l y 2 p p m /ma, whic h r e s u l t s in a n er r o r o f 2.5 p p m (12.5 v) fo r th e 1.25 ma c u r r en t dra w n f r o m i t . this co r r es p o n d s t o a 0. 164 ls b er r o r . f i g u re 31. r e f19 5 as p o wer sup p l y t o a d 56 60 bipolar operation using the ad5660 the ad5660 has been desig n e d f o r sin g le-s u p p l y o p era t io n b u t a b i p o la r o u t p ut ra n g e is als o p o s s i b le usin g t h e cir c ui t in f i gur e 32. th e c i r c ui t b e lo w wi l l g i v e a n o u t p u t v o lt ag e ra n g e o f 5 v . r a i l -t o-rai l o p e r a t io n a t t h e am plif ier o u t p u t is achie v ab le using a n ad820 o r a n o p 295 as th e ou t p u t a m p l if ier . the o u t p u t v o l t a g e fo r a n y i n p u t co de c a n b e ca lc u l a t e d as fol l o w s: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = 1 2 1 2 1 65536 r r v r r r d v v dd dd o w h er e d r e p r es en ts t h e in p u t c o de in decimal (0C65535). w i t h v dd = 5 v , r 1 = r 2 = 10 k?: v d v o 5 65536 10 ? ? ? ? ? ? ? = this is an o u t p u t v o l t a g e ran g e o f 5 v wi th 00 00h ex co r r es po n d in g to a ?5 v o u t p u t a n d ffff h e x co r r es po n d in g to a + 5 v out p ut . f i gure 32. bipolar o p er at ion with the ad5660 using ad5660 with an opto-isolated interface i n p r o c ess - con t r o l a p plica t io n s in i n d u st r i a l e n vir o n m e n t s i t is of te n ne c e ss ar y to u s e an opto - i s o l a t e d i n te r f ac e to prote c t and i s o l a t e t h e c o n t r o l l i ng c i rc u i t r y f rom an y h a z a rd ou s c o m m o n - m o de v o l t a g es th a t ma y occur i n th e a r ea w h e r e th e d a c i s f u nc t i on i n g . o p to - i s o l a tor s prov i d e i s o l a t i o n i n e x c e ss of 3 k v . b e ca us e the ad5660 us es a thr e e-wir e s e r i al log i c in t e r f ace , i t re qu i r e s on ly t h re e opto - i s o l a to r s to prov i d e t h e re qu i r e d is o l a t io n (s ee f i gur e 33). th e p o w e r s u p p l y t o th e p a r t als o n e e d s t o b e is ol a t e d . this is don e b y usin g a t r a n sfo r m e r . on t h e d a c s i d e of t h e t r ans f or me r , a 5 v re g u l a tor pr ov i d e s t h e 5 v s u p p l y r e q u ir ed f o r th e ad5660 . f i gure 3 3 . ad56 60 wi th a n o p to -isol a t e d inter f ac e
ad5660 preliminary technical data rev. prj page 18 of 20 power supply bypassing and grounding when accuracy is important in a circuit it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5660 should have separate analog and digital sections, each having its own area of the board. if the ad5660 is in a system where other devices require an agnd to dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5660. the power supply to the ad5660 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physically as close as possible to the device with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and effective series inductance (esi), for example, common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board.
prelim inary technical data ad5660 r e v. prj | pa ge 19 o f 20 outline dimensions f i g u re 34. 8-l e ad s o t - 23 (rj-8) f i g u re 35. 8-l e ad m s op (rj-8) ordering guide m o d e l g r a d e p o w e r - o n - r e s e t t o internal reference branding package options 1 d e s c r i p t i o n AD5660ARJ-1 a zero 1.25 v tbd rj-8 32 lsb inl, 25 ppm/c ref, 3 v ad5660arj-2 a zero 2.5 v tbd rj-8 32 lsb inl, 25 ppm/c ref, 5 v a d 5 6 6 0 a r j - 3 a m i d s c a l e 2 . 5 v t b d rj-8 32 lsb inl, 25 ppm/c ref, 5 v ad5660brj-1 b zero 1.25 v tbd rj-8 16 lsb inl, 25 ppm/c ref, 3 v ad5660brj-2 b zero 2.5 v tbd rj-8 16 lsb inl, 25 ppm/c ref, 5 v a d 5 6 6 0 b r j - 3 b m i d s c a l e 2 . 5 v t b d rj-8 16 lsb inl, 25 ppm/c ref, 5 v ad5660crm-1 c zero 1.25 v tbd rm-8 16 lsb inl, 10 ppm/c ref, 3 v ad5660crm-2 c zero 2.5 v tbd rm-8 16 lsb inl, 10 ppm/c ref, 5 v ad5660crm-3 c midscale 2.5 v tbd rm-8 16 lsb inl, 10 ppm/c ref, 5 v 1 rj = sot-23 r m = mso p
ad5660 prelim inary technical data rev. prj page 20 of 20 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . pr04539-0-5/04(pr j)

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